The market demand for non-volatile memories with higher and higher memory capacity imposes on the manufacturers of semiconductors a continuous effort in the reduction of the dimension of the devices and in the increase of the density of stored data.
In order to increase the information storage capacity in a flash memory, that is, in memory cells that maintain their programming state even in the absence of the supply voltage, without necessarily decreasing the physical dimensions of the single cells, the cells must be programmed in such a way that they are able to memorize more than one bit of information, that is the memory cell must be able to have m=2.sup.n different states or programming levels, where n represents the number of bits that can be memorized in the memory cell. This cell is called "multilevel memory cell", where each level corresponds to a different value of the threshold voltage of the transistor making up the cell.
The discrimination of the different m programming levels requires a greater precision in the operations of writing and reading. The stage of writing is realized, for instance, in a such way that memory cell is programmed in one of the different m levels by adequately adjusting its threshold voltage in such a way that, when the memory cell is biased at the desired threshold, during the stage of reading, said cell absorbs a corresponding power at the pre-established level of threshold voltage.
Two reading techniques have been proposed for multilevel memory cells: parallel reading and serial reading.
The parallel reading provides for the generation of m-1 predetermined and distinct reference voltages or currents (current references for the current approach, or voltage references for the voltage approach) and the execution of m-1 simultaneous comparisons of such m-1 distinct reference voltages or currents with a current (or a voltage) derived from the memory cell that is to be read.
The advantages of this technique are the high speed and the independence of the reading time from the programming state of the memory cell; a disadvantage is the large area required by the reading circuit, because m-1 separate comparison circuits are necessary to carry out the m-1 simultaneous comparisons.
The serial reading, instead, requires one single reference (current or voltage) that can be varied according to the prescribed law. This single reference is used in order to carry out a series of subsequent comparisons, and it is varied in order to approximate the voltage or the current that is derived from the memory cell that must be read. The advantage of this technique is that it has a simple circuit realization and the area required is small.
It is evident that the time required for the reading of a memory cell is not uniform, but it depends on the particular programming level of the memory cell and on the starting value of the reference voltage (or current) (the reading time depends on the distance between the programming level of the cell that is to be read and the starting value of the reference voltage or current): in order to determine the programming state of a memory cell at m levels a minimum of one to a maximum of m-1 steps of comparison can be necessary. The reading time soon becomes excessive with the increase of the number of bits that are memorized in a single memory cell.
Therefore, it becomes necessary to speed up all the operations of writing, reading and erasing in such a way that it is possible to meet the specifications of the internationally defined standards for the realization of bulk storage devices that replace the magnetic disk.
In particular a cause for the slowing in the operation of writing is the stage of the verification. In fact, this stage, in addition to providing adequate programming pulses, consists in the continuous control of the value of the threshold voltage that is obtained, while verifying that it is the desired one, after a certain number of pulses have been applied to same cell.
The number of verifications depends on the programming algorithm that is used. In an verification algorithm of the "programming and verification pulse" type (suitable to the multilevel programming of floating gate non-volatile memory cells), the operation of control is carried out after each programming pulse. Instead, by increasing the complexity of the circuitry it is possible to compare directly or indirectly the voltage drop between the gate and source electrodes of the memory cell, which is the value of the memorized voltage threshold, with the desired voltage value, while decreasing the number of verifications to be carried out in order to determine the memorization state of the memory cell.
The operation of reading of the threshold voltage value is equivalent to the operation of verification of the threshold voltage value and therefore the time for the reading of the stored datum coincides with the time for the verification of the stored datum.
It is thus evident that the faster the operation of verification will be, the quicker it will be possible to program the cell.